1. Technical Field
This invention relates in to a field effect device having an channel of carbon nanofabric and a method of making the same.
2. Discussion of Related Art
Scaling of CMOS FETs is increasingly difficult, even at the 90 nm technology node, with high leakage currents resulting in high standby power dissipation at short channel lengths due to well-known problems associated with scaling FET devices threshold voltages. In large measure this scaling problem is caused by the difficulty in gate control of the electrical characteristics of the FET channel region in the silicon substrate. The problem is expected to get much worst as technology dimensions shrink to 65 nm, 45 nm, and 20 nm values. There is concern that scaling below 20 nm using silicon substrates may become impractical from both technical feasibility and a fabrication cost perspectives.
The operating principle of the metal oxide semiconductor field effect transistors, (MOSFETS) is very well understood; see S. M. Sze, Semiconductor Devices: Physics and Technology (John Wiley and Sons, New York, 1985. In general, a field effect transistor has a source region, a drain region and a channel region disposed between the source and drain. The conductivity of a region of semiconducting material of the channel is modulated by an adjacent, electrically isolated structure (the gate). When the gate is electrically charged, a conduction pathway in the semiconductor is either created or eliminated which is the basis of an electrically controlled switch. FETs form the basis for logic, memory and analog applications in the electronics industry. The industry strives to fabricate these devices such that they can operate faster, consume less power and consume less space: the latter leads to greater functionality for a given surface area.
Smaller FETs than those made using silicon based sources, drains and channels have been proposed which utilize individual carbon nanotubes, either doped or undoped, as channel regions. See Derycke, V. et al., “Carbon Nanotube Inter- and Intramolecular Logic Gates,” Nano Letters, Vol. 1 No. 9, 453-456. Such channel region nanotubes must be individually placed between sources and drains, and therefore the fabrication of a single ultra dense array would be prohibitively time consuming if not impossible.
Currently there are nanotube-based FET devices under development at various academic laboratories. Devices reported in the literature include thin dielectric layers to maximize gate coupling to the nanotube. See 2. V. Derycke, et al., Controlling doping and carrier injection in carbon nanotube transistors, Applied Physics Letters, Vol. 80, No. 15, Apr. 15, 2002, A. Javey, et. al., High-k Dielectrics for Advanced Carbon-nanotube Transistors and Logic Gates, from a nature materials Online Publication, Nov. 17, 2002 and S. J. Wind, J., et al., Vertical scaling of carbon nanotubes field-effect transistors using top gate electrodes. Applied Physics Letters, Vol. 80, No. 20, May 20, 2002.
One of the problems with current fabrication techniques is that there does not exist a method for consistently aligning one or more nanotubes (NTs) with other components of a given device.
Research has shown that individual (single) semiconducting single-walled nanotubes (SWNTs) exhibit high electron and hole mobility (higher than those in silicon substrates) and reduced short channel effects, see Seidel, Nano Letters Chen, J., “Self-Aligned Carbon Nanotube Transistors with Novel Chemical Doping,” IEEE 2004; Lin, Y.-M., “Novel Carbon Nanotube FET Design with Tunable Polarity,” IEEE 2004; Avouris, Ph., et al., “Carbon Nanotube Electronics and Optoelectronics,” IEEE 2004; Guo, J., et al., “Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts and High-K Gate Dielectrics,” Javey, A. et al., “Carbon Nanotube Field-Effect Transistors With Integrated Ohmic Contacts and High-k Gate Dielectrics,” Nano Lett. 2004, Vol. 4, No. 3, 447-450. Reduced short channel effects are likely due to the surface conduction of the SWNT fibers. That is, the FET channel remains at the surface of the SWNT fiber. While research has demonstrated individual (single) semiconducting SWNT operation for P-type, N-type, and Ambipolar-type FET devices, useful carbon nanotube FET (CNFET) devices must be optimized and integrated into a process flow that includes placement, patterning, and wiring of CNFET devices. CNFET devices may have a selectable number multiple SWNTs in parallel for increase current flow and higher performances required for product design. Since both metallic and semiconducting SWNTs are present when using nanotube wafer-growth techniques or wafer spin-on techniques, it is necessary to selectively eliminate metallic SWNT from the CNFET devices. Finally, the electrical characteristics of the CNFET devices must be optimized for operation in the voltage range required for product design.
Prior Art Dual-Gate FET Device Operation and Characteristics:
In the mid to late 1960's, PMOS-based products with non-self-aligned aluminum gates became available. PMOS had the advantage that when fabricated the devices were in the normally OFF state, with no channel between the P+ source—drain regions. PMOS devices had negative threshold voltages and operated between ground and minus VDD (−VDD). Threshold voltages were high, −5 volts for example, and VDD applied voltages were in the −12 to −20 V range. Also, the mobility was 2.5 to 3× lower than NMOS mobility. Threshold voltages were reduced with PMOS device scaling. The difference in mobility between PMOS and NMOS devices remain due to the relative mobilities of p-type and n-type carriers in the FET channel region. FIGS. 1A and 1A1 show a cross section of a prior art PMOS FET (PFET) 10 and associated I-V characteristic.
There was strong interest in using N-type FETs because of much lower NMOS channel resistance for the same geometries due to the superior electron mobility, 2.5 to 3× higher than PFET hole mobility. Bipolar circuits (TTL) were operating at positive 5 volts power supply so there was strong interest in FET products operating with positive 5 volt power supply for ease of mixing new FET-based products with the existing bipolar technology. A major problem was that NMOS devices were in the ON state as fabricated. Positive ions both fixed and mobile, combined with the work function of the aluminum gate and p-substrate doping, plus defects in the Si/SiO2 interface made it impossible to find a fabrication-only solution to the fabricated normally-ON NMOS problem (it took well over 10 years to find a fabrication-only solution). Products designers needed a way to use normally-ON NMOS FETs or remain with an inferior P-type FET technology. The NFET problem of these prior art devices is described in the text book by J. Millman & C. Halkias, “Integrated Electronics: Analog and Digital Circuits and Systems,” McGraw-Hill Book Company, 1972, pages 322-328.
Prior art FIG. 2A shows the cross section of early NMOS devices normally ON as fabricated and associated I-V characteristics in FIG. 2A1, with the NMOS having a negative threshold voltage. Prior art FIG. 2B cross section and associated FIG. 2B1 show the operation of the device using a signal VSIG applied between source S and gate G. The gate to source voltage must be negative to modulate the channel region to eliminate a depletion region between the channel the surface (Si—SiO2 interface). This method of operation could not meet the requirement of operating voltages in the zero to VDD range, with a positive threshold voltage. Prior art FIG. 2C cross section and associated FIG. 2C1 I-V characteristics shows the effect of introducing a substrate bias voltage VBIAS that is used to electrostatically alter the electrical properties of the channel region. Using the substrate as common back-gate biased negative with respect to NFET source diffusions, the normally-ON FET channel resulting from process-only fabrication techniques was turned OFF and NFET threshold voltage was set using electrostatic coupling in the depletion region between the substrate region and the channel region. The electrical I-V characteristic of FIG. 2B1 was translated to the electrical characteristic shown in FIG. 2C1 using VBIAS. The NFET gate G voltage operating range for NFET product design was in the 0 to 5 volt range (5 volt power supply compatible), achieved using a combination of process (chemical) means and electrostatic (electrical) means as illustrated in prior art FIG. 2C. Signal Vsig may now operate in the positive 0 to 5 volts range, for example.